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Espressif Systems /ESP32-C3 /RTC_CNTL /INT_CLR_RTC

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Interpret as INT_CLR_RTC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLP_WAKEUP_INT_CLR)SLP_WAKEUP_INT_CLR 0 (SLP_REJECT_INT_CLR)SLP_REJECT_INT_CLR 0 (WDT_INT_CLR)WDT_INT_CLR 0 (BROWN_OUT_INT_CLR)BROWN_OUT_INT_CLR 0 (MAIN_TIMER_INT_CLR)MAIN_TIMER_INT_CLR 0 (SWD_INT_CLR)SWD_INT_CLR 0 (XTAL32K_DEAD_INT_CLR)XTAL32K_DEAD_INT_CLR 0 (GLITCH_DET_INT_CLR)GLITCH_DET_INT_CLR 0 (BBPLL_CAL_INT_CLR)BBPLL_CAL_INT_CLR

Description

rtc configure register

Fields

SLP_WAKEUP_INT_CLR

Clear sleep wakeup interrupt state
SLP_REJECT_INT_CLR

Clear sleep reject interrupt state
WDT_INT_CLR

Clear RTC WDT interrupt state
BROWN_OUT_INT_CLR

Clear brown out interrupt state
MAIN_TIMER_INT_CLR

Clear RTC main timer interrupt state
SWD_INT_CLR

Clear super watch dog interrupt state
XTAL32K_DEAD_INT_CLR

Clear RTC WDT interrupt state
GLITCH_DET_INT_CLR

Clear glitch det interrupt state
BBPLL_CAL_INT_CLR

clear bbpll cal end interrupt state

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd